Implementing an all-digital PHY and delay- locked loop for high-speed DDR2/3 memory interfaces

A high-speed DDR2, DDR2/3, or DDR3 DRAM interface for off-chip memory provides a powerful tool to meet the high-performance demands of new electronic products. However, with advancements come new challenges. The DDR DRAM high-speed interface between the system-on-chip (SoC) and off-chip memory requires specialty circuits. These circuits, often referred to as a physical layer (PHY), comprise high-speed I/Os; a high-resolution, high-precision delay lock loop (DLL); and specialty high-speed logic (PHY logic) to manage the data transfers between the SoC and off-chip DRAM.